The article by T. C. Denk et al entitled “Reconfigurable hardware for efficient implementation of programmable FIR filters” published in ISCASSP, May 1998, described a finite impulse response filter architecture which enables to anticipate the calculation of a filter result before the arrival of the last data included in this result. For this purpose, the data already received are stored in view of being used in an anticipated intermediate calculation for the calculation of the current final result. This method implies that the speed of calculation of the filter processor is synchronized with the receiving speed of the data.